The background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
The amount of information archived on computer storage is constantly increasing. Sorting through increasing amounts of information can be incredibly time-consuming for even the most advanced computer systems without systems and methods for optimizing methods to transport data. Every element of data processing needs to be optimized and streamlined to prevent bottlenecks
A common bottleneck of data processing is sending/receiving data from remote systems, particularly if several processors or threads need to use a single common buffer to transmit data to a remote system.
U.S. Pat. No. 5,566,175 to Davis teaches a broadband telecommunications system that maximizes bandwidth utilization with a FIFO buffer by reserving a larger bandwidth when there is more data to transfer and a smaller bandwidth when there is lesser data to transfer. Davis' system, however, is not useful in increasing data flow when a plurality of threads are using the same shared buffer for transport, and a plurality of threads are waiting for a first thread to transmit data before transmitting their data.
U.S. Pat. No. 7,397,809 to Wang teaches an improved combined switching data unit queuing discipline, that uses a plurality of FIFO queues of a hybrid output port, allowing for a plurality of threads to be spread among several FIFO queues. Wang's system, however, still forces a fast thread to wait for a slow thread if the fast thread happens to be unluckily placed behind a slow thread.
U.S. Pat. No. 7,733,889 to Katayama teaches a network switching device that prevents a blocking problem by dividing received packets into multiple fixed length packets and supplying them to a buffer. In this manner, if a slow thread happens to be transmitting data slower than a fast thread, then the slow thread does not slow down the fast thread as much since the fast thread is able to transmit its data as soon as one fixed length packet is transmitted by the slow thread. Katayama's system, however, still forces a fast thread to wait until the slow thread completes at least one fixed length packet's worth of transmission before accepting data from the fast thread.
Thus, there remains a need for a system and method to improve the throughput and transmission of data from multiple sources through a single bottleneck.